| [News] Transcript of Alan Redhouses speech at AmiGBG 2003 | ANN.lu |
| Posted on 31-Mar-2003 19:40 GMT by Peter Gordon | 54 comments
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I have transcribed Alans AmiGBG speech. It can be viewed here.
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| Transcript of Alan Redhouses speech at AmiGBG 2003 : Comment 48 of 54 | ANN.lu |
| Posted by IanG on 03-Apr-2003 10:10 GMT | In reply to Comment 42 (Anonymous):
>>Motorola and IBM *who designed the chip we're talking about* probably do have a
>>fairly good clue about cache system designs. And they say you should see 3%.
>Again - where does IBM say that?
>Apple is (was?) part of AIM alliance and has the most experience when it comes
>to desktop computer systems (MOT concentrates on embedded appliances).
OK. I am going by the comment that was made in Alan's speech which said their inability to achieve much speed gain from the L3 resulted in Mot/IBM(?) saying that was what they expected. It is entirely possible that Alan misinterpreted what was said or has misrepresented the situation, or maybe I've misunderstood what he said.
> Apple say on http://www.apple.com/powermac/architecture.html :
> "L3 cache keeps the PowerPC G4’s engine stoked
Well, yes, I'm sure Apple, just as any other company, will squeeze every marketing opportunity out of "extra" hardware or features, whether they exist to truly beneift or just to overcome shortcomings.
> L3 cache is high-speed Double Data Rate memory. It provides fast access to
> data and application code through a dedicated bus to the processor [....]
The description is little more than a description of any generic cache system. I had assumed (feel free to correct me) that an L3 cache system exists in addition to an L2 cache, or that the tests that Alan refer to are relative between an L3 and L2 (or other) cache system. Not the lack of any cache whatsoever. |
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