| [News] Marvell announces Discovery III Northbridge | ANN.lu |
| Posted on 30-Sep-2003 15:01 GMT by takemehomegrandma | 94 comments
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Marvell today announced the Discovery III northbridge. It features a 200MHz PowerPC CPU interface, 200MHz DDR SDRAM Interface (400Mbps data rate), Dual CPU SMP Support (MPX and 60x modes), PCI-X, Gigabit ethernet and is software compatible with other Discovery northbridges.
Source: morphos-news.de
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| Marvell announces Discovery III Northbridge : Comment 68 of 94 | ANN.lu |
| Posted by Joe "Floid" Kanowitz on 01-Oct-2003 12:04 GMT | In reply to Comment 64 (Crumb // AAT):
> I haven't said the contrary, but it would be a greater step if motorola or
> ibm decided to add DDR support to its range of g3/G4s...
Okay, come off it, guys. The *throughput* of the bus is what matters in selecting a memory technology, not the clocking. Half the point of *having* a northbridge (in conventional, non-integrated designs) is to tie the CPU to memory that, these days, is almost always going to be completely unrelated, be it as simple as an asynchronous clocking or as complex as a move to MRAM or the next big miracle technology.
To approach the theoretical maximum of a single-rate 200MHz bus, you'd need 200MHz single-rate SDRAM, which doesn't exist on the common market. The DDR nomenclature that revolves around clock rates (DDR333, DDR400...) is the mythical number - DDR333 runs at 166MHz. So you 'only' waste 133 mythical MHz, which probably help drive down latencies, keep the caches packed and prevent PCI/AGP from starving the CPU anyway.
Sure, it'd be great to have stonkingly faster CPU buses, and DDR and QDR have been the way to achieve them for now. But that's just one popular variety of 'magic,' and DDR and QDR on the CPU have nothing direct to do with DDR and QDR on the SDRAM.
Whine about the throughputs and latencies, please, not the pixie dust. If you set out to redesign the 60x/MPX buses for DDR (which they were supposed to have been doing with MPX+ on the never-unveiled? G4 MPC7470) and require a reworking of all northbridges anyway, you may as well ditch the old protocol and move to something more scalable overall. (Which they've done; 970 uses the ApplePI 'Elastic Bus,' allowing per-CPU links to the memory controller; the enlightened side of the x86 camp went NUMA and HyperTransport, and so on.)
That's harsh, I'm overcaffeinated. Again, it'd be wonderful if they made chips that supported perfect, future-proof FSBs, but the fact is they don't, and one assumes they would if it were as easy or economical as we all wish it were. We all know the answer, we just don't like to hear it -- the only way to help that situation is by growing the market and making it more worthwhile for the designers to overcome the hurdles. If the performance crown is all that matters, well... you can get three computers for the price of a computer, these days. Six if you count Hyperthreading. |
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