[Forum] Try only to realise the truth | ANN.lu |
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Try only to realise the truth : Comment 226 of 335 | ANN.lu |
Posted by Chris Hodges on 06-Jul-2004 09:30 GMT | In reply to Comment 225 (Johan Rönnblom): I really don't know what people are arguing about. This is my personal view (!) based on my technical knowledge:
During DMA transfers, the ArticiaS does not flag accessed memory as "dirty", therefore the CPU does not automatically know, that it has to update/flush its caches (and Kjetil, the MMU and its associated tables keep track of which pages are cachable and which are not). This is no problem for AmigaOS, given that the old hardware did not support automatic cache invalidation. Hence, CachePreDMA()/CachePostDMA() were introduced for Kickstart2.0, when it was obvious, that DMA capable components would need a mechanism to invalidate certain cachelines in the CPU manually. If all drivers are written with this manual software cache coherence in mind, this is no problem. Therefore I do not assume a problem for AmigaOS4, as this CachePreDMA()/CachePostDMA() should still work as proposed.
This is, however, a problem for other operating systems (such as Linux?), which rely on automatic hardware cache line invalidation/flushing for DMA accessed memory. If the operating system does not allow such fine-granular cache flushing, the whole cache has to be flushed. This bad for L1 cache, but is a heavy speed penalty for L2/L3 caches (remember, they're *big*). Still, working drivers would be possible. If the driver runs in user-space and the OS does not provide cache control at all: game over.
As the hardware DMA support is assumed for most systems, hardly anybody will care for such manual cache consistency in their drivers. So although this might be possible to fix for Linux, I don't think every driver will be checked for necessary CachePreDMA and CachePostDMA calls.
Even if one would not call the ArticiaS bugged related to DMA, it is clearly a missing feature for transparent DMA operations. |
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