[Forum] Try only to realise the truth | ANN.lu |
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Try only to realise the truth : Comment 243 of 335 | ANN.lu |
Posted by Chris Hodges on 06-Jul-2004 11:40 GMT | In reply to Comment 240 (Ferry): Just to avoid some misunderstandings, here's the DMA issue as I understand it:
Case 1:
Assume you want to read a block from disk to memory. With non-coherent cache, the following could happen: DMA transfers the data to memory. Now the CPU tries to read from that space and already has some bits (or all of it) in its cache! But the CPU does not know that the cached data is now invalid and has benn replaced by some new data. Therefore, the CPU will use the cached, possibly old data and not the freshly read disk block.
Case 2:
Assume you want to write a block from memory to disk. Without cache coherency, DMA will start to transfer the data to disk, without knowing, if the memory has been updated with the correct data. The CPU still might have some data in its caches (usually, the data has been worked on recently, so the CPU has kept it in the cache), because it might be configured to Copyback (not Writethrough) and the memory still contains some of the old, unmodified data. The block on the disk therefore will contain old, possibly corrupt data after the DMA operation.
CachePre/PostDMA informs the CPU to flush the caches after the DMA operation (case 1) or mark the cached lines as dirty (case 2).
With bussnooping DMA cache coherency, this is not needed, as the CPU will be informed about it on the fly. |
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