[Forum] Try only to realise the truth | ANN.lu |
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Try only to realise the truth : Comment 248 of 335 | ANN.lu |
Posted by Bernie Meyer on 06-Jul-2004 13:31 GMT | In reply to Comment 247 (Bernie Meyer): And just before someone points out that writing into your DMA memory during the transfer results in undefined behaviour, anyway, here is a scenario in which pre- and post-DMA invalidating of cachelines is not sufficient to avoid inconsistent behaviour:Scenario A: DMA the data "abcd" into memory range ABCD, in that order. While that transfer is in progress, CPU wites first to "x" C, then to "y" B. Possible outcomes with coherency: "abcd" (if the writes precede the actual DMA), "aycd" (if the write of "x" precedes DMA to C, but the write of "y" comes after the DMA to B), "ayxd" (if both writes happen after the DMA has been done for B and C).Now, if the cache gets explicitly invalidated prior to DMA as well as after the DMA, there is a chance that during the time DMA is done for D, none, one, or both of the CPU-written areas B and C are write-backed from cache to memory. And the problem occurs when C does get written back, but B doesn't. You then end up with "abxd", which is not possible in a properly coherent system.Worse yet, you can run into the same kind of problem without having the CPU write. Scenario B: DMA the data "abcd" into the memory range ABCD, which previously held "wxyz". While the transfer is going, have the CPU execute alternate reads from B and C. In a cache-coherent system, as soon as you have read "c" from C, you will *never* read "x" from B, because the fact that C has been updated implies that B has been updated.In a non-cache-coherent system, however, in which you invalidate caches at the start and the end of DMA, the CPU accesses will pull both B and C into the CPU cache. If at any time the cacheline for C is flushed, while the cacheline for B isn't, you can end up reading "c" from C yet afterwards still read "x" from B.Once again, you *can* get around these issues by using bounce buffers (dedicated temporary memory into which DMA is done, and from which the CPU then copies the data into its ultimate destination) --- but pumping each byte of "DMA'ed" data through the CPU, even memory-to-memory, is hardly the point of DMA. |
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