[Forum] Try only to realise the truth | ANN.lu |
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Try only to realise the truth : Comment 312 of 335 | ANN.lu |
Posted by Anonymous on 07-Jul-2004 13:56 GMT | Short extract from Articia S documentation published by Mai Logic:
"The snoop cycle is used to probe the primary and secondary cache for updated data when the PCI
accesses DRAM. This is done to maintain data coherency between the Floating Buffer, DRAM and both
caches. The Articia S performs the Snoop cycle. When there is a snoop hit on a modified cache line in
either level one or two cache, the contents are written back directly to the Floating Buffer. A PCI Bus
master can subsequently later on fetch the data directly from the Floating Buffer. The Floating Buffer is
flushed back to DRAM during a PCI write cycle. The corresponding line in level one or level two cache is
thus invalidated. Snoops are hidden, meaning the CPU can continue its current data access without
being interrupted while the Articia S simultaneously queries both caches."
The design is fine. The ArticiaS should maintain cache coherency during PCI Bus master access (that is DMA).
But that doesn't work... and it is a serious bug.
The real question is: why do Hyperion&Eyetech people say the documentation is fine but bplan people didn't know how to read it? |
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