[Forum] Try only to realise the truth | ANN.lu |
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Try only to realise the truth : Comment 319 of 335 | ANN.lu |
Posted by hammer on 07-Jul-2004 21:04 GMT | In reply to Comment 313 (Fabio Alemagna): "SNDF2003_DALLAS_A2513.pdf" has some hints of it e.g. in Page 18....
- copy and paste -
Floating Buffer
* Patented Floating Buffer design
provides tag-fixed, data floated
buffering technology
* Quickly handles buffered data
from bus-to-bus for data
coherency control
* 256-bit point-to-point data bus
structure for easy data path
connection and layout design
* Thread cache for concurrent CPU,
AGP, and PCI to DRAM access
* Piped control engine for coherent
maintenance
* Pre-fetch, Merge Write and Page
Re-ordering support
* Threading control to optimize
performance for different devices
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From Page 20
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Articia’s Cache Coherency Flow
* If snoop miss, the device needs to request data from
DRAM again
n Lower performance with extra request cycles when snoop
miss
* Higher performance with concurrent processing of snoop
operation and DRAM data requesting
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Note that this is from MAI's marketing matterials. |
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