[Unmoderated] ArticiaS: mystery finaly solved ? | ANN.lu |
Posted on 08-Jul-2004 06:47 GMT by brotheris | 140 comments View flat View list |
Here's the summary of the last posts from hot topic. It may finaly put some dots on I's. Up to now we have heared a lot of small bits from variuos parties and finaly we can put the puzzle together. Read more about it.
I'll play Amon_Re of the past:
It all started when Chris Hogdes started explaining few things (in this thread and @226 comment).
During DMA transfers, the ArticiaS does not flag accessed memory as "dirty", therefore the CPU does not automatically know, that it has to update/flush its caches
Later (@ comment 247, 248 and others) Bernie Meyer explained how such a lack of feature (or call it a bug) affects stability, performance and may cause data corruption even in AmigaOS-like enviroment while using CachePreDMA()/CachePostDMA().
And then we discover quotes from ArticiaS documentation:
"The snoop cycle is used to probe the primary and secondary cache for updated data when the PCI
accesses DRAM. This is done to maintain data coherency between the Floating Buffer, DRAM and both
caches. The Articia S performs the Snoop cycle. When there is a snoop hit on a modified cache line in
either level one or two cache, the contents are written back directly to the Floating Buffer. A PCI Bus
master can subsequently later on fetch the data directly from the Floating Buffer. The Floating Buffer is
flushed back to DRAM during a PCI write cycle. The corresponding line in level one or level two cache is
thus invalidated. Snoops are hidden, meaning the CPU can continue its current data access without
being interrupted while the Articia S simultaneously queries both caches."
You can find similar information using google cache. It seems like some people lied. Is lack of Cache Coherency a bug or a feature (it was advertised that there is Cache Coherency, so it had to work) ? We may now put this case to rest.
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ArticiaS: mystery finaly solved ? : Comment 109 of 140 | ANN.lu |
Posted by Johan Rönnblom on 11-Jul-2004 15:04 GMT | In reply to Comment 107 (Sammy Nordström): Sammy wrote:
> I mean, if there really is such fault in the hardware, why not help
> MAI solve it?
They offered to help, Gerald staid for weeks working with MAI's
engineers, but in the end MAI weren't very cooperative.
Let's face it Sammy, it's not like either bPlan or Tratech were
neutral on this issue. They *relied* on MAI. They had invested a lot
of time and effort in a product based on their chips. They didn't want
to find bugs in them. But despite this, they did - at great expense
for themselves.
> First of all, you are not the one to turn to for recommendations
> about the AmigaOne to begin with, period.
Why not? Who is the one to turn to, then?
I think I'm fairly neutral on this issue, let's compare the parties
involved:
Genesi: I've done business with them, or rather with Thendic France,
but unfortunately it turned sour, as after the bankruptcy I didn't get
the money we had agreed upon. I have never bought a product by them.
bPlan: No business or customer relation. Eyetech: No business or
customer relation. MAI: No business or customer relation.
Hyperion: I've bought a couple of their games.
So yes, I think I'm perfectly able to form my opinion solely on the
merits of the respective products here. Also, note that I'm not saying
that no one should buy an A1.
About making claims about bugs in the Pegasos computers, of course,
please go ahead. If you do know something, tell us. I'm quite sure
that most Pegasos users would be quite interested, at least that's my
experience thus far when problems have been found. |
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