[Unmoderated] ArticiaS: mystery finaly solved ? | ANN.lu |
Posted on 08-Jul-2004 06:47 GMT by brotheris | 140 comments View flat View list |
Here's the summary of the last posts from hot topic. It may finaly put some dots on I's. Up to now we have heared a lot of small bits from variuos parties and finaly we can put the puzzle together. Read more about it.
I'll play Amon_Re of the past:
It all started when Chris Hogdes started explaining few things (in this thread and @226 comment).
During DMA transfers, the ArticiaS does not flag accessed memory as "dirty", therefore the CPU does not automatically know, that it has to update/flush its caches
Later (@ comment 247, 248 and others) Bernie Meyer explained how such a lack of feature (or call it a bug) affects stability, performance and may cause data corruption even in AmigaOS-like enviroment while using CachePreDMA()/CachePostDMA().
And then we discover quotes from ArticiaS documentation:
"The snoop cycle is used to probe the primary and secondary cache for updated data when the PCI
accesses DRAM. This is done to maintain data coherency between the Floating Buffer, DRAM and both
caches. The Articia S performs the Snoop cycle. When there is a snoop hit on a modified cache line in
either level one or two cache, the contents are written back directly to the Floating Buffer. A PCI Bus
master can subsequently later on fetch the data directly from the Floating Buffer. The Floating Buffer is
flushed back to DRAM during a PCI write cycle. The corresponding line in level one or level two cache is
thus invalidated. Snoops are hidden, meaning the CPU can continue its current data access without
being interrupted while the Articia S simultaneously queries both caches."
You can find similar information using google cache. It seems like some people lied. Is lack of Cache Coherency a bug or a feature (it was advertised that there is Cache Coherency, so it had to work) ? We may now put this case to rest.
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ArticiaS: mystery finaly solved ? : Comment 116 of 140 | ANN.lu |
Posted by Anonymous on 12-Jul-2004 08:07 GMT | In reply to Comment 111 (Sammy Nordström): Cache coherency is a property which means that software running on the CPU can pretend that the cache doesn't exist and it will just work. If you read values, and they happen to come from the cache, they will be the same values that you would have got from RAM, and if you write values and they're written to the cache, they will have the same effect as if they'd been written to RAM.
Without cache coherency all operations that might change the contents of RAM must be accompanied by countermeasures (in software) to ensure that the cached values are either discarded or properly updated. An example of such an operationg would be a DMA transfer, in which data is copied from say the hard disk controller into RAM, without direct supervision by the CPU.
So on Pentium PC, or an Apple Mac, or whatever your programs just do a DMA transfer, and when it finishes everything is hunky-dory, very fast and efficient. The work needed to update caches is done transparently in hardware.
But if cache coherency is not present, or if it's BROKEN then you need to manually invalidate the cache somehow, or ensure that the DMA transfer is done to and from (obviously slower) non-cached RAM. Bernie Meyer described these scenarios a year or so back and Ben Hermans agreed that they were what the OS4 team intended...
Problems of this sort aren't particularly rare, you might see one new design each year, especially in hardware not originally intended for high performance work, which has such a defect purely by accident. The defect is fatal to high performance work, without a workaround data is corrupted, and the workaround savages performance. |
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