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[News] C=1 status update, "Introducing JRISC, the new early startup processor"ANN.lu
Posted on 23-Feb-2004 17:55 GMT by takemehomegrandma9 comments
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I know this news item is old in date, but it seems like it has not been posted here yet (and I know that a lot of ann readers are interested in this project), so:

Here's the long-awaited news update after many months of intense work on the C-One. We were so close to releasing the boards with a working C64 core, but there was something that kept us from completing the early startup procedure: The size of the design. It simply did not fit in the "small" FPGA, the 1K30 that launches the whole system.

Many weeks of optimizing freed a few logic cells, but did not make the design fit. Taking a bigger FPGA was not an option, because the boards had already been produced a long time ago. Exchanging the FPGAs on 300 boards (where some of them are already spread all around the globe at the developer's sites) would have been too costly, and too risky for those who want to do it on their own. Exchanging a 208-pin QFP package is something you can do at home, but you should have lots of experience and the right tools.

We dropped the idea of a bigger FPGA. This would have been the Wintel way of doing things: If it does not work, use a bigger/faster computer. We're Commodore people, and that means we're taking hardware restrictions as a challenge, not as a limit of our brains.

The lion share of logic cells was eaten up by the 6502 processor, AKA the drive CPU. Although it's cut-down version with no BCD support has gotten 50% smaller than any other implementation you can find on the net, it was still too big to be fitted with the D-Ram controller, the video controller, keyboard controller, floppy controller, audio engine and the early startup DMA engine that gets the 64K of early startup code into the memory.

The other parts of the design are as small as can be. Neither a memory controller, nor video or the DMA engine can be considered "big". It's the CPU that takes up too much space, so Jeri tried to optimize that, and having squeezed everything out of it, it was clear that the 6502 had to go.

The new idea was to create a microcode engine that loads a 6502 emulator with the DMA engine. A new processor from scratch. During the design phase, Jeri discovered that the microcode engine she designed was nearly a full processor. Just add a few things here and there, cut out the microcode overhead, and all of a sudden we have a RISC processor, the JRISC. Even the DMA engine can be wiped, because the CPU has a small bootstrap that can load it's code from the flash memory.

Before anyone complains about not having the 6502 any more, and all the work on that being done in vain: We still need the 6502 for the C64 "compatibility" core. The work was necessary, we're glad it's done, and we're confident that this implementation of a 6502 on an FPGA beats any other in size, speed and cycle-exact execution. It's just that the 6502 is not used in early startup any more, but the C64 will of course stay with this classic processor, and the "native C-One" will stay with the 65816, as promised in all the technical data that has been spread over the course of the project.

The text continues here (lots more to read): http://c64upgra.de/c-one/jrisc.htm

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