Here's the summary of the last posts from hot topic. It may finaly put some dots on I's. Up to now we have heared a lot of small bits from variuos parties and finaly we can put the puzzle together. Read more about it.
I'll play Amon_Re of the past:
It all started when Chris Hogdes started explaining few things (in this thread and @226 comment).
During DMA transfers, the ArticiaS does not flag accessed memory as "dirty", therefore the CPU does not automatically know, that it has to update/flush its caches
Later (@ comment 247, 248 and others) Bernie Meyer explained how such a lack of feature (or call it a bug) affects stability, performance and may cause data corruption even in AmigaOS-like enviroment while using CachePreDMA()/CachePostDMA().
And then we discover quotes from ArticiaS documentation:
"The snoop cycle is used to probe the primary and secondary cache for updated data when the PCI
accesses DRAM. This is done to maintain data coherency between the Floating Buffer, DRAM and both
caches. The Articia S performs the Snoop cycle. When there is a snoop hit on a modified cache line in
either level one or two cache, the contents are written back directly to the Floating Buffer. A PCI Bus
master can subsequently later on fetch the data directly from the Floating Buffer. The Floating Buffer is
flushed back to DRAM during a PCI write cycle. The corresponding line in level one or level two cache is
thus invalidated. Snoops are hidden, meaning the CPU can continue its current data access without
being interrupted while the Articia S simultaneously queries both caches."
You can find similar information using google cache. It seems like some people lied. Is lack of Cache Coherency a bug or a feature (it was advertised that there is Cache Coherency, so it had to work) ? We may now put this case to rest.
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