Posted on 01-Jan-2004 20:24 GMT by ID4 - tHe SuRvIvOr - | 73 comments View flat View list |
AGPx8, DDR2, MPEG4 ..... Are some of the new Articia I chipset features!!! Link here
AGPx8, DDR2, MPEG4 ..... Are some of the new Articia I chipset features!!! Link here
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Articia I : Comment 44 of 73 | ANN.lu |
Posted by Kjetil on 03-Jan-2004 00:31 GMT | In reply to Comment 41 (Matt Parsons): What evidence? the data corruption can only to be found whit the DMA enabled on the via chipset, the rest of the time my computer is stable,
there for the issue given from Ben/Hyperion for the fault is more then good, to explain the problem, the Articia S chipset will need to cashe the data flow while writing or reading form the other source, an data bus can not be really be accessed at once by tow end points, how ever the delay time can be improved by improving the efficiency in how it's used, this what I think that call "Bus-Centric-Architecture", http://www.mai.com/products/BRA660R2.0.pdf well if you read the few lines about it says it out of spec; "more balanced architecture serving both CPU and peripheral bus requirements then the traditinal "CPU-Centric" design approach"
if that type cashing conflict whit dma, DMA will try to request data by it's own, and there for conflict whit the articia S caches, data output may end up being the wrong bits of data, so the solution to the problem will be that via drivers need to flush/fill cache cache at right time when Articia S is ready to read/write data, or disable the DMA. The Via driver might expect an transparent bus (not waiting for a ready state on the bus), and that is not what Articia S requires. Aritica S requires cooperation to work whit DMA.
the problem will be when the Articia cache is filled whit some data, and the DMA tryes accessing it when it's not ready.
the Pegasus fix might be that the via chipset is chip select or clock signal being disabled while Articia busy, or some thing similar; how ever that approach effects alott of things, one might expect some DMA devices to fail, it the drivers fail to fetch data when thay think the DMA is ready. |
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