|[News] Pictures of the MicroA1 "Industrial" motherboard||ANN.lu|
|Posted on 17-Oct-2004 12:25 GMT by Not ArticiaP||69 comments|
On this link you will see three pictures of the MicroA1 "Industrial" motherboard: http://lain.ziaspace.com/~ryu/a1. On the pictures you can see that it still uses the ArticiaS northbridge, as well as the VIA 686B southbridge, but a standalone Sil0680 IDE controller is there as well.
|List of all comments to this article|
|Pictures of the MicroA1 "Industrial" motherboard : Comment 33 of 69||ANN.lu|
|Posted by Anonymous (126.96.36.199) on 19-Oct-2004 00:19 GMT|
|In reply to Comment 16 (Adam Kowalczyk):|
> WRT PCI BUS 0, a PLD was added to allow 6 bus masters. The PCI 104 slot is on BUS 0.
What was the main idea of including this PLD chip?
A) To solve problems with ArticiaS and VT82C686B communication? (VIA ATA-100 controller problems in UDMA mode)
If this PLD fixes this problem why additional ATA controller (Sil 0680) has been added on the uA1-I board?
If this PLD does not solve this problem why Sil 0680 are not present on the uA1-C board? Isn't it because C version was designed earlier, when VIA ATA-100 controller problem wasn't known?
B) Only for adding 6 (instead of 5 supported by Articia S) bus masters devices to BUS-0?
If yes, why support for only 6 bus master has been added? Why not 7?
Support for 6 devices only means that one PCI device (RTL8110 NIC controller) had to be placed on BUS-1. It means that BUS-1 have to be configured as 66MHz PCI without the AGP features. This downgrades Radeon 7000 capabilities from AGP x2 to AGP x0 (= PCI).
Why they did it? Because Articia S do not support AGP x2 features in spite of MAI claims?
|List of all comments to this article (continued)||